Semiconductor memory device and method of manufacturing the same
US10546871B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 12, 2016 |
| Grant date | Jan 28, 2020 |
| Priority date | — |
| Expiry date | Nov 28, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/27
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device according to an embodiment comprises: a memory cell array region including a plurality of conductive layers that are electrically connected to a plurality of memory cells arranged in a first direction on a semiconductor substrate, the first direction intersecting a surface of the semiconductor substrate; a stepped part for contacting the plurality of conductive layers to a wiring line; a contact extending in the first direction and being connected to the conductive layer in the stepped part; and a plurality of columnar bodies extending in the first direction and penetrates the conductive layer in the stepped part and including a first columnar body having a first height and a second columnar body having a second height which is lower than the first height.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.