Semiconductor memory device having a channel structure vertically passing through a plurality of memory layers and having memory cell blocks and dummy memory cell blocks
US10546874B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2017 |
| Grant date | Jan 28, 2020 |
| Priority date | — |
| Expiry date | Mar 30, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device including a substrate including a first block and a second block each having a cell array region and a connection region, a stack including insulating layers and gate electrodes and extending from the cell array region to the connection region, first cell channel structures in the cell array region of the first block and passing through the stack to be electrically connected to the substrate, first dummy channel structures in the connection region of the first block and passing through the stack, second cell channel structures in the cell array region of the second block and passing through the stack, and second dummy channel structures in the connection region of the second block and passing through the stack may be provided. The first dummy channel structures are electrically insulated from the substrate, while the second dummy channel structures are electrically connected to the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.