Structures and methods for noise isolation in semiconductor devices
US10546937B2 · kind B2 · utility
6Cited by
7References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2018 |
| Grant date | Jan 28, 2020 |
| Priority date | — |
| Expiry date | Jul 13, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/215
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a semiconductor structure includes a substrate with a top surface and first and second devices formed on the top surface of the substrate. The semiconductor structure also includes a deep isolation structure formed in the substrate and between the first and second devices. The deep isolation structure includes a top portion formed at the top surface and having a top width and a bottom surface having a bottom width larger than the top width.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.