Gulbagh Singh
46Patents
3h-index
18Co-inventors
52Inventor score
Filing activity: Jul 6, 2017 → Jan 29, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10748911B2 | Integrated circuit for low power SRAM | Electricity | 7 | Active |
| US10790391B2 | Source/drain epitaxial layer profile | Electricity | 6 | Active |
| US10546937B2 | Structures and methods for noise isolation in semiconductor devices | Electricity | 6 | Active |
| US10672795B2 | Bulk semiconductor substrate configured to exhibit semiconductor-on-insulator behavior | Electricity | 3 | Active |
| US10163831B2 | Semiconductor device with post passivation structure and fabrication method therefor | Electricity | 2 | Active |
| US11335638B2 | Reducing RC delay in semiconductor devices | Electricity | 2 | Active |
| US10886165B2 | Method of forming negatively sloped isolation structures | Electricity | 2 | Active |
| US11404537B2 | Semiconductor device with air-void in spacer | Electricity | 1 | Active |
| US11817345B2 | Multiple thickness semiconductor-on-insulator field effect transistors and methods of forming the same | Electricity | 1 | Active |
| US11183570B2 | Structures and methods for noise isolation in semiconductor devices | Electricity | 1 | Active |
| US10734489B2 | Method for forming semiconductor device structure with metal silicide layer | Electricity | 1 | Active |
| US11417749B2 | Semiconductor arrangement with airgap and method of forming | Electricity | 1 | Active |
| US11887987B2 | Semiconductor wafer with devices having different top layer thicknesses | Electricity | 1 | Active |
| US11367778B2 | MOSFET device structure with air-gaps in spacer and methods for forming the same | Electricity | 1 | Active |
| US12027581B2 | Semiconductor device with air-void in spacer | Electricity | 1 | Active |
| US11804439B2 | Reducing RC delay in semiconductor devices | Electricity | 1 | Active |
| US11462642B2 | Source/drain epitaxial layer profile | Electricity | 1 | Active |
| US11855137B2 | SOI device structure for robust isolation | Electricity | 0 | Active |
| US11257902B2 | SOI device structure for robust isolation | Electricity | 0 | Active |
| US12211934B2 | Semiconductor structure and method for manufacturing the same | Electricity | 0 | Active |
| US12199181B2 | Semiconductor structure and method for manufacturing the same | Electricity | 0 | Active |
| US12191196B2 | Method of manufacturing a metal-oxide-semiconductor field-effect transistor (MOSFET) having low off-state capacitance | Electricity | 0 | Active |
| US10636870B2 | Isolation regions for reduced junction leakage | Electricity | 0 | Active |
| US11810879B2 | Semiconductor structure including buffer layer | Electricity | 0 | Active |
| US11348944B2 | Semiconductor wafer with devices having different top layer thicknesses | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.