Method for manufacturing a resistive random access memory; having reduced variability of electrical characteristics
US10547002B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 7, 2017 |
| Grant date | Jan 28, 2020 |
| Priority date | — |
| Expiry date | Oct 18, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing resistive random access memories, each resistive random access memory including first and second electrodes separated by a layer of active material, the method including producing connector elements with a step Cp along a first direction, each connector element having a width Cb along the first direction; producing a plurality of first electrodes with a step Ep along the first direction, each first electrode having a first end surface and a second end surface, the second end surface having a width Eb along the first direction and an area greater than the area of the first end surface; wherein:
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.