Peripheral component interconnect express (PCIE) network with input/output (I/O) chaining to reduce communication time within execution of I/O channel operations
US10552054B2 · kind B2 · utility
1Cited by
5References
19Claims
0Family size
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Key dates
| Filing date | Jul 2, 2018 |
| Grant date | Feb 4, 2020 |
| Priority date | — |
| Expiry date | Jul 2, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A set of memory access operations is obtained. The set of memory access operations includes a plurality of memory access operations to be chained, in which the plurality of memory access operations are to be processed as an atomic unit. The plurality of memory access operations are executed in a particular order, and one or more results are provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.