Software-assisted instruction level execution preemption
US10552202B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 12, 2017 |
| Grant date | Feb 4, 2020 |
| Priority date | — |
| Expiry date | May 12, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/46
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment of the present invention sets forth a technique for instruction level execution preemption. Preempting at the instruction level does not require any draining of the processing pipeline. No new instructions are issued and the context state is unloaded from the processing pipeline. Any in-flight instructions that follow the preemption command in the processing pipeline are captured and stored in a processing task buffer to be reissued when the preempted program is resumed. The processing task buffer is designated as a high priority task to ensure the preempted instructions are reissued before any new instructions for the preempted context when execution of the preempted context is restored.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.