Christopher Lamb
10Patents
3h-index
15Co-inventors
53Inventor score
Filing activity: May 10, 2007 → Nov 7, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8180998B1 | System of lanes of processing units receiving instructions via shared memory units for data-parallel or task-parallel operations | Physics | 12 | Active |
| US7627744B2 | External memory accessing DMA request scheduling in IC of parallel processing engines according to completion notification queue occupancy level | Physics | 10 | Active |
| US9513975B2 | Technique for computational nested parallelism | Physics | 7 | Active |
| US10552201B2 | Software-assisted instruction level execution preemption | Physics | 2 | Active |
| US9575760B2 | Techniques for sharing priorities between streams of work and dynamic parallelism | Physics | 2 | Active |
| US9652282B2 | Software-assisted instruction level execution preemption | Physics | 2 | Active |
| US10725837B1 | Persistent scratchpad memory for data exchange between programs | Physics | 2 | Active |
| US10915364B2 | Technique for computational nested parallelism | Physics | 0 | Active |
| US9483423B2 | Techniques for assigning priorities to memory copies | Physics | 0 | Active |
| US10552202B2 | Software-assisted instruction level execution preemption | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.