Corrupt logical block addressing recovery scheme
US10552243B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 12, 2017 |
| Grant date | Feb 4, 2020 |
| Priority date | — |
| Expiry date | Mar 16, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B20/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Technology for handling page size mismatches when DPL-CLR is performed at multiple levels of a data storage system (for example, RAID level and flash card level). A “corrective DPL” corrects only a portion of the data that would make up a page at the level at which the data is stored (that is, the “initial DPL level”), and, after that, a partially corrected page of data is formed and stored in data storage, with the partially corrected page: (i) having a page size characteristic of the initial DPL; (ii) including the part of the data corrected by the corrective DPL; and (iii) further including other data. In some embodiments, the other data has a pattern that indicates that it is invalid, erroneous data, such that an error message will be returned if this portion of the data is attempted to be read.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.