Fault-tolerant power-driven synthesis
US10552740B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 10, 2014 |
| Grant date | Feb 4, 2020 |
| Priority date | — |
| Expiry date | Mar 24, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention relate to providing fault-tolerant power minimization in a multi-core neurosynaptic network. In one embodiment of the present invention, a method of and computer program product for fault-tolerant power-driven synthesis is provided. Power consumption of a neurosynaptic network is modeled as wire length. The neurosynaptic network comprises a plurality of neurosynaptic cores connected by a plurality of routers. At least one faulty core of the plurality of neurosynaptic cores is located. A placement blockage is modeled at the location of the at least one faulty core. A placement of the neurosynaptic cores is determined by minimizing the wire length.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.