Reducing memory latency in graphics operations
US10552934B2 · kind B2 · utility
1Cited by
0References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2016 |
| Grant date | Feb 4, 2020 |
| Priority date | — |
| Expiry date | Apr 15, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus relating to reducing memory latency in graphics operations are described. In an embodiment, uniform data is transferred from a buffer to a General Register File (GRF) of a processor based at least in part on information stored in a gather table. The uniform data comprises data that is uniform across a plurality of primitives in a graphics operation. Other embodiments are also disclosed and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.