Semiconductor memory device
US10553276B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 26, 2018 |
| Grant date | Feb 4, 2020 |
| Priority date | — |
| Expiry date | Mar 10, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3436
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory cell array, a first data latch that retains a write unit of data to be written to the memory cell array, a first address latch that retains a write address indicating a write target destination for the write unit of data in the first data latch, a second data latch that retains fail data that is a write unit of data that has failed to be written to the memory cell array, and a second address latch that retains a fail address indicating a write target destination for the fail data. A controller is configured to output the fail address from the second address latch in response to a first output command requesting output of the fail address and to output the fail data from the second data latch in response to a second output command requesting an output of the fail data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.