Interconnects containing serpentine line structures for three-dimensional memory devices and methods of making the same
US10553537B2 · kind B2 · utility
0Cited by
6References
12Claims
0Family size
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Key dates
| Filing date | Feb 17, 2018 |
| Grant date | Feb 4, 2020 |
| Priority date | — |
| Expiry date | Feb 17, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8828
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device structure includes an array of semiconductor devices located in an array region over a substrate, metal lines laterally extending from the device region to a peripheral interconnection region, and interconnect via structures located in the peripheral interconnection region, and contacting a portion of a respective one of the plurality of metal lines. The metal lines include a first metal line and a second metal line each having a serpentine region which contacts a respective interconnect via structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.