Memory cell including a plurality of wells
US10553597B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 24, 2018 |
| Grant date | Feb 4, 2020 |
| Priority date | — |
| Expiry date | Dec 24, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/66
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory cell includes a first transistor coupled to a source line, wherein the first transistor is in a first well. The memory cell further includes a second transistor coupled to the first transistor and a bit line, wherein the second transistor is in the first well. The memory cell further includes a first capacitor coupled to a word line and the second transistor, wherein the first capacitor is in a second well. The memory cell further includes a second capacitor coupled to the second transistor and an erase gate, wherein the second capacitor is in the second well. In some embodiments, the first well contacts the second well on a first side of the first well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.