Hau-Yan Lu
45Patents
5h-index
33Co-inventors
65Inventor score
Filing activity: Mar 22, 2007 → Feb 27, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8174063B2 | Non-volatile semiconductor memory device with intrinsic charge trapping layer | Electricity | 62 | Active |
| US8344445B2 | Non-volatile semiconductor memory cell with dual functions | Electricity | 11 | Active |
| US8638589B2 | Operating method for non-volatile memory unit | Electricity | 7 | Active |
| US9620594B2 | Memory device, memory cell and memory cell layout | Electricity | 6 | Active |
| US9384815B2 | Mechanisms for preventing leakage currents in memory cells | Physics | 6 | Active |
| US8724363B2 | Anti-fuse memory ultilizing a coupling channel and operating method thereof | Electricity | 4 | Active |
| US9431107B2 | Memory devices and methods of manufacture thereof | Electricity | 3 | Active |
| US8390056B2 | Non-volatile semiconductor memory device with intrinsic charge trapping layer | Electricity | 2 | Active |
| US9537016B1 | Memory device, gate stack and method for manufacturing the same | Electricity | 2 | Active |
| US8604538B2 | Non-volatile semiconductor memory device with intrinsic charge trapping layer | Electricity | 1 | Active |
| US10163920B2 | Memory device and memory cell | Electricity | 1 | Active |
| US9257522B2 | Memory architectures having dense layouts | Physics | 1 | Active |
| US8363475B2 | Non-volatile memory unit cell with improved sensing margin and reliability | Physics | 1 | Active |
| US9711516B2 | Non-volatile memory having a gate-layered triple well structure | Physics | 1 | Active |
| US8456916B2 | Non-volatile memory unit cell with improved sensing margin and reliability | Physics | 1 | Active |
| US11940659B2 | Optical integrated circuit structure including edge coupling protective features and methods of forming same | Electricity | 1 | Active |
| US11977256B2 | Semiconductor package comprising optically coupled IC chips | Physics | 0 | Active |
| US10553597B2 | Memory cell including a plurality of wells | Electricity | 0 | Active |
| US12140796B2 | Frequency- and process-insensitive splitting use multiple splitters in series | Physics | 0 | Active |
| US11251314B2 | Memory devices and methods of manufacture thereof | Electricity | 0 | Active |
| US10043919B2 | Memory devices and methods of manufacture thereof | Electricity | 0 | Active |
| US11892681B2 | Fiber to chip coupler and method of making the same | Physics | 0 | Active |
| US12422623B2 | Two-dimensional grating coupler and method of forming the same | Physics | 0 | Active |
| US11869991B2 | Semiconductor device and method of making | Electricity | 0 | Active |
| US10510902B2 | Memory devices and methods of manufacture thereof | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.