Semiconductor device having buried gate structure, method for manufacturing the same, and memory cell having the same
US10553692B2 · kind B2 · utility
3Cited by
1References
16Claims
0Family size
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Key dates
| Filing date | Jul 12, 2016 |
| Grant date | Feb 4, 2020 |
| Priority date | — |
| Expiry date | Aug 4, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
Abstract
A semiconductor device includes at least one trench extending into a semiconductor substrate and lined with a gate dielectric layer; a dipole inducing layer covering a lowermost portion of the lined trench; a gate electrode covering the dipole inducing layer and filled in the lined trench; and doping regions, in the semiconductor substrate, separated from each other by the lined trench and separated from the dipole inducing layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.