QE approach by double-side, multi absorption structure
US10553733B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2017 |
| Grant date | Feb 4, 2020 |
| Priority date | — |
| Expiry date | Sep 27, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/8063
Abstract
The present disclosure relates to an integrated chip that has a light sensing element arranged within a substrate. An absorption enhancement structure is arranged along a back-side of the substrate, and an interconnect structure is arranged along a front-side of the substrate. A reflection structure includes a dielectric structure and a plurality of semiconductor pillars that matingly engage the dielectric structure. The dielectric structure and semiconductor pillars are arranged along the front-side of the substrate and are spaced between the light sensing element and the interconnect structure. The plurality of semiconductor pillars and the dielectric structure are collectively configured to reflect incident light that has passed through the absorption enhancement structure and through the light sensing element back towards the light sensing element before the incident light strikes the interconnect structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.