Sequential logic circuitry with reduced dynamic power consumption
US10558188B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 2019 |
| Grant date | Feb 11, 2020 |
| Priority date | — |
| Expiry date | May 21, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/56
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Digital systems formed on integrated circuits may include sequential logic circuitry. The sequential logic circuitry may form at least part of a finite state machine that records different logical states. The sequential logic circuitry may include a first latching circuit and a second latching circuit that each latch bits onto their respective outputs when clocked at different levels. The first latching circuit may output a first bit. Combinational logic circuitry may be distributed on both sides of the first latching circuit such that a combinational logic circuit interposed between the first and second latching circuits generates a second bit based on at least the first bit. The first and second bits may record one of two possible finite logical states of the sequential logic circuitry. By distributing combinational logic circuity on two sides of a given latching circuit, dynamic power consumption by the sequential logic circuitry may be optimized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.