Daniel Firu
16Patents
3h-index
10Co-inventors
49Inventor score
Filing activity: Apr 14, 2014 → Sep 26, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10839378B1 | Systems and methods for performing device authentication operations using cryptocurrency transactions | Physics | 14 | Active |
| US9942046B2 | Digital currency mining circuitry with adaptable difficulty compare capabilities | Electricity | 3 | Active |
| US11270298B2 | Digital currency mining circuitry | Electricity | 3 | Active |
| US9659123B2 | Systems and methods for flexibly optimizing processing circuit efficiency | Physics | 2 | Active |
| US10409827B2 | Digital currency mining circuitry having shared processing logic | Emerging Cross-Sectional Technologies | 1 | Active |
| US10338558B2 | Sequential logic circuitry with reduced dynamic power consumption | Electricity | 1 | Active |
| US11301481B2 | Digital currency mining circuitry having shared processing logic | Emerging Cross-Sectional Technologies | 1 | Active |
| US10761848B1 | Systems and methods for implementing core level predication within a machine perception and dense algorithm integrated circuit | Physics | 1 | Active |
| US12063291B2 | Devices and circuitry for computing hash values | Electricity | 1 | Active |
| US11755806B2 | Systems and methods for executing a programmable finite state machine that accelerates fetchless computations and operations of an array of processing cores of an integrated circuit | Physics | 0 | Active |
| US11087067B2 | Systems and methods for implementing tile-level predication within a machine perception and dense algorithm integrated circuit | Physics | 0 | Active |
| US11392667B2 | Systems and methods for an intelligent mapping of neural network weights and input data to an array of processing cores of an integrated circuit | Physics | 0 | Active |
| US10558188B2 | Sequential logic circuitry with reduced dynamic power consumption | Electricity | 0 | Active |
| US11714556B2 | Systems and methods for accelerating memory transfers and computation efficiency using a computation-informed partitioning of an on-chip data buffer and implementing computation-aware data transfer operations to the on-chip data buffer | Physics | 0 | Active |
| US11526877B2 | Electronic devices having embedded circuitry for accessing remote digital services | Electricity | 0 | Active |
| US11061678B1 | Systems and methods for optimizing nested loop instructions in pipeline processing stages within a machine perception and dense algorithm integrated circuit | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.