Methods and systems for distributing memory requests
US10558573B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2018 |
| Grant date | Feb 11, 2020 |
| Priority date | — |
| Expiry date | Sep 11, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/608
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory request, including an address, is accessed. The memory request also specifies a type of an operation (e.g., a read or write) associated with an instance (e.g., a block) of data. A group of caches is selected using a bit or bits in the address. A first hash of the address is performed to select a cache in the group. A second hash of the address is performed to select a set of cache lines in the cache. Unless the operation results in a cache miss, the memory request is processed at the selected cache. When there is a cache miss, a third hash of the address is performed to select a memory controller, and a fourth hash of the address is performed to select a bank group and a bank in memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.