Inventor · Sutton, MA, US

David Asher

44Patents
10h-index
40Co-inventors
75Inventor score

Filing activity: Apr 3, 1998 → Mar 20, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US6633960B1 Scalable directory based cache coherence protocol Physics 49 Expired
US6681295B1 Fast lane prefetching Physics 36 Expired
US7213087B1 Mechanism to control the allocation of an N-source shared buffer Electricity 35 Expired
US6212493A Profile directed simulation used to target time-critical crossproducts during random vector testing Physics 28 Expired
US6654858B1 Method for reducing directory writes and latency in a high performance, directory-based, coherency protocol Physics 24 Expired
US6148427A Method and apparatus for test data generation Physics 20 Expired
US6671822B1 Method and system for absorbing defects in high performance microprocessor with a large n-way set associative cache Physics 14 Expired
US7941585B2 Local scratchpad and data caching system Physics 13 Expired
US7606998B2 Store instruction ordering for multi-core processor Physics 13 Expired
US5878054A Method and apparatus for test data generation Physics 11 Expired
US10282299B2 Managing cache partitions based on cache usage information Physics 10 Active
US8595401B2 Input output bridging Physics 6 Active
US8473658B2 Input output bridging Physics 6 Active
US9870328B2 Managing buffered communication between cores Physics 6 Active
US6918015B2 Scalable directory based cache coherence protocol Physics 6 Expired
US9501425B2 Translation lookaside buffer management Physics 5 Active
US9355206B2 System and method for automated functional coverage generation and management for IC design protocols Physics 5 Active
US9026312B2 Ergonomics test buck Fixed Constructions 4 Active
US9665505B2 Managing buffered communication between sockets Physics 3 Active
US7370151B2 Method and system for absorbing defects in high performance microprocessor with a large n-way set associative cache Physics 3 Expired
US11036643B1 Mid-level instruction cache Physics 3 Active
US9372800B2 Inter-chip interconnect protocol for a multi-chip system Physics 3 Active
US11093405B1 Shared mid-level data cache Physics 2 Active
US9058463B1 Systems and methods for specifying. modeling, implementing and verifying IC design protocols Physics 2 Active
US9612934B2 Network processor with distributed trace buffers Physics 2 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.