Method of enabling a partial reconfiguration in an integrated circuit device
US10558777B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 22, 2017 |
| Grant date | Feb 11, 2020 |
| Priority date | — |
| Expiry date | Mar 19, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of implementing a partial reconfiguration in an integrated circuit device is described. The method comprises reading a netlist for a design of a circuit comprising a reconfigurable module; defining a first region of the integrated circuit device having the reconfigurable module; defining a second region that encompasses the first region; placing the reconfigurable module of the design in the first region, wherein the reconfigurable module comprises a partition pin of a plurality of available partition pins; selectively removing the partition pin; routing drivers and loads that are in the second region; and generating a partial bitstream for the reconfigurable module.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.