Circuit topology of memory chips with embedded function test pattern generation module connected to normal access port physical layer
US10559374B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2017 |
| Grant date | Feb 11, 2020 |
| Priority date | — |
| Expiry date | Mar 11, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory chip architecture includes a plurality of test pads, a plurality of interface pads, a function block and an embedded test block. The function block is coupled to the interface pads. The embedded test block is coupled to the test pads. The embedded test block is connected to an access port physical layer (PHY) through the interface pads. The interface pads are disposed between the function block and the embedded test block. The embedded test block is arranged for generating at least one test pattern as a test signal, and outputting the test signal to the function block through the interface pads to test the function block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.