PieceMakers Technology, Inc.
13Patents
13Active
13Granted
46Portfolio score
Filing activity: Mar 2, 2012 → Jan 5, 2022
Most-cited patents
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US11183231B2 | Apparatus for enhancing prefetch access in memory module | Physics | 3 | Active |
| US11437087B2 | Method and apparatus for accumulating and storing respective access counts of word lines in memory module | Physics | 1 | Active |
| US9466355B2 | Memory architecture dividing memory cell array into independent memory banks | Physics | 1 | Active |
| US10634713B2 | Method for testing semiconductor die pad untouched by probe and related test circuit | Physics | 1 | Active |
| US8754656B2 | High speed test circuit and method | Physics | 0 | Active |
| US9653148B1 | Multi-bank memory device and system | Physics | 0 | Active |
| US9997224B2 | Memory architecture with multi-bank memory cell array accessed by local drive circuit within memory bank | Physics | 0 | Active |
| US11755685B2 | Apparatus for data processing in conjunction with memory array access | Physics | 0 | Active |
| US11721390B2 | DRAM with inter-section, page-data-copy scheme for low power and wide data access | Physics | 0 | Active |
| US11393547B2 | Anti-fuse one-time programmable memory cell and related array structure | Electricity | 0 | Active |
| US11250904B1 | DRAM with inter-section, page-data-copy scheme for low power and wide data access | Physics | 0 | Active |
| US10559374B2 | Circuit topology of memory chips with embedded function test pattern generation module connected to normal access port physical layer | Physics | 0 | Active |
| US9679622B2 | Method for controlling memory device asynchronously with respect to system clock, and related memory device and memory system | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.