Self-aligned quadruple patterning process for Fin pitch below 20nm
US10559501B2 · kind B2 · utility
0Cited by
5References
14Claims
0Family size
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Key dates
| Filing date | Sep 20, 2016 |
| Grant date | Feb 11, 2020 |
| Priority date | — |
| Expiry date | Sep 20, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/853
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of producing a FinFET device with fin pitch of less than 20 nm is presented. In accordance with some embodiments, fins are deposited on sidewall spacers, which themselves are deposited on mandrels. The mandrels can be formed by lithographic processes while the fins and sidewall spacers formed by deposition technologies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.