Memory device and forming method thereof
US10559592B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2018 |
| Grant date | Feb 11, 2020 |
| Priority date | — |
| Expiry date | Sep 10, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/7684
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate and a first alternating conductor/dielectric stack disposed on the substrate and a dielectric layer disposed over the first alternating conductor/dielectric stack. A second alternating conductor/dielectric stack is disposed on the dielectric layer. The NAND memory device includes one or more array common source contacts extending orthogonally with respect to the surface of the substrate through the first layer stack and the second layer stack, wherein at least one of the one or more array common source contacts includes a first conductive contact and a second conductive contact that is disposed over and electrically connected with the first conductive contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.