Secure memory arrangements
US10560263B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 31, 2017 |
| Grant date | Feb 11, 2020 |
| Priority date | — |
| Expiry date | Mar 6, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/76
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Various examples are directed to secure memory arrangements and methods of using the same. A gateway device of the secure computing system may receiving a first message from an external system. The first message may comprise a first message payload data and first asymmetric access data. The gateway device may determine that the first asymmetric access data matches the first message payload data based at least in part on an external system public key. The gateway device may access a first system controller symmetric key associated with a first system controller in communication with the gateway device and generate a first symmetric access data based at least in part on the first system controller symmetric key and the first message payload data. The gateway device may send the first message payload data and the first symmetric access data to the first system controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.