Synchronization in a multi-tile processing arrangement
US10564970B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 1, 2018 |
| Grant date | Feb 18, 2020 |
| Priority date | — |
| Expiry date | Mar 13, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/084
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing system comprising multiple tiles and an interconnect between the tiles. The interconnect is used to communicate between a group of some or all of the tiles according to a bulk synchronous parallel scheme, whereby each tile in the group performs an on-tile compute phase followed by an inter-tile exchange phase with the exchange phase being held back until all tiles in the group have completed the compute phase. Each tile in the group has a local exit state upon completion of the compute phase. The instruction set comprises a synchronization instruction for execution by each tile upon completion of its compute phase to signal a sync request to logic in the interconnect. In response to receiving the sync request from all the tiles in the group, the logic releases the next exchange phase and also makes available an aggregated a state of all the tiles in the group.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.