Placement, routing, and deadlock removal for network-on-chip using integer linear programming
US10565346B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2017 |
| Grant date | Feb 18, 2020 |
| Priority date | — |
| Expiry date | Feb 3, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Implementing a circuit design can include generating an integer linear programming (ILP) formulation for a routing problem by determining constraints for implementing nets of a circuit design within a programmable network-on-chip (NOC) of an integrated circuit, wherein the constraints include placement constraints and routability constraints for the nets. The nets can be simultaneously placed and routed by executing an ILP solver using a processor to minimize an objective function of the ILP formulation while observing the constraints. The ILP solver maps logical units of the nets to interface circuits of the programmable NOC concurrently with mapping the nets to channels of the programmable NOC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.