Deep junction electronic device and process for manufacturing thereof
US10566189B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 31, 2017 |
| Grant date | Feb 18, 2020 |
| Priority date | — |
| Expiry date | May 31, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/268
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a process for manufacturing a deep junction electronic device including steps of: b) Depositing a layer of non-monocrystalline semiconductor material on a plane surface of a substrate of a monocrystalline semiconductor material; c) Incorporating inactivated dopant elements prior to step b) into said substrate (1) and/or, respectively, during or after step b) into said layer, so as to form an inactivated doped layer; d) Exposing, an external surface of the layer formed at step b) to a laser thermal anneal beam, so as to melt said layer down to the substrate and so as to activate said dopant elements incorporated at step c); e) Stopping exposure to the laser beam so as to induce epi-like crystallization of the melted layer, so that said substrate and/or, respectively, an epi-like monocrystalline semiconductor material, comprises a layer of activated doped monocrystalline semiconductor material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.