Mark structure for aligning layers of integrated circuit structure and methods of forming same
US10566291B2 · kind B2 · utility
0Cited by
2References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2018 |
| Grant date | Feb 18, 2020 |
| Priority date | — |
| Expiry date | Feb 18, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/54453
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
This disclosure relates to a structure for aligning layers of an integrated circuit (IC) structure that may include a first dielectric layer positioned above a semiconductor substrate having one or more active devices, a trench stop layer positioned above the first dielectric layer, a second dielectric layer positioned above the trench stop layer, and a plurality of metal-filled marking trenches extending vertically through the second dielectric layer and the trench stop layer and at least partially into the first dielectric layer. The metal-filled trenches are electrically isolated from any active devices contained in the IC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.