Dielectric separation of partial GAA FETs

US10566330B2 · kind B2 · utility

Assignee

• SAMSUNG ELECTRONICS CO., LTD. · KR

Inventors

• Mark S. Rodder · Dallas, US
• Borna J. Obradovic · Leander, US
• Dharmendar Reddy Palle · Austin, US
• Rwik Sengupta · Austin, US
• Mohammad Ali Pourghaderi · Heverlee, BE

Key dates

• Filing date: May 11, 2018
• Grant date: Feb 18, 2020
• Expiry date: May 11, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/85
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

A CMOS system on chip including a series of partial gate-all-around field effect transistors. Each partial GAA FET includes a fin having a stack of channel regions, source and drain regions on opposite sides of the fin, a dielectric separation region including a dielectric material between first and second channel regions, a gate stack on the fin, and a pair of sidewall spacers on opposite sides of the gate stack. A portion of the dielectric separation region has a length from an outer edge of the dielectric separation region to an inner edge of a respective sidewall spacer. The length of the portion of the dielectric separation region of one of the partial GAA FETs is different than the length of the portion of the dielectric separation region of another one of the partial GAA FETs.