Borna J. Obradovic
82Patents
12h-index
37Co-inventors
84Inventor score
Filing activity: Dec 28, 2002 → Apr 10, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9287357B2 | Integrated circuits with Si and non-Si nanosheet FET co-integration with low band-to-band tunneling and methods of fabricating the same | Emerging Cross-Sectional Technologies | 65 | Active |
| US9570609B2 | Crystalline multiple-nanosheet strained channel FETs and methods of fabricating the same | Electricity | 48 | Active |
| US9461114B2 | Semiconductor devices with structures for suppression of parasitic bipolar effect in stacked nanosheet FETs and methods of fabricating the same | Performing Operations; Transporting | 42 | Active |
| US9490323B2 | Nanosheet FETs with stacked nanosheets having smaller horizontal spacing than vertical spacing for large effective width | Electricity | 33 | Active |
| US9647098B2 | Thermionically-overdriven tunnel FETs and methods of fabricating the same | Electricity | 33 | Active |
| US9711414B2 | Strained stacked nanosheet FETS and/or quantum well stacked nanosheet | Electricity | 31 | Active |
| US9812449B2 | Multi-VT gate stack for III-V nanosheet devices with reduced parasitic capacitance | Electricity | 29 | Active |
| US9853114B1 | Field effect transistor with stacked nanowire-like channels and methods of manufacturing the same | Electricity | 21 | Active |
| US10026652B2 | Horizontal nanosheet FETs and method of manufacturing the same | Electricity | 19 | Active |
| US9466669B2 | Multiple channel length finFETs with same physical gate length | Electricity | 15 | Active |
| US9741811B2 | Integrated circuit devices including source/drain extension regions and methods of forming the same | Electricity | 13 | Active |
| US9484423B2 | Crystalline multiple-nanosheet III-V channel FETs | Electricity | 12 | Active |
| US9905672B2 | Method of forming internal dielectric spacers for horizontal nanosheet FET architectures | Electricity | 11 | Active |
| US10878317B2 | Method and system for performing analog complex vector-matrix multiplication | Physics | 10 | Active |
| US9793403B2 | Multi-layer fin field effect transistor devices and methods of forming the same | Electricity | 9 | Active |
| US9653287B2 | S/D connection to individual channel layers in a nanosheet FET | Electricity | 9 | Active |
| US10566330B2 | Dielectric separation of partial GAA FETs | Electricity | 8 | Active |
| US9178045B2 | Integrated circuit devices including FinFETS and methods of forming the same | Electricity | 7 | Active |
| US9831323B2 | Structure and method to achieve compressively strained Si NS | Electricity | 7 | Active |
| US9960232B2 | Horizontal nanosheet FETs and methods of manufacturing the same | Electricity | 7 | Active |
| US8119470B2 | Mitigation of gate to contact capacitance in CMOS flow | Emerging Cross-Sectional Technologies | 6 | Active |
| US7537988B2 | Differential offset spacer | Electricity | 6 | Active |
| US9013167B2 | Hall effect device having voltage based biasing for temperature compensation | Physics | 6 | Active |
| US10164121B2 | Stacked independently contacted field effect transistor having electrically separated first and second gates | Electricity | 5 | Active |
| US7727838B2 | Method to improve transistor Tox using high-angle implants with no additional masks | Electricity | 4 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.