Three-dimensional semiconductor memory device and method of fabricating the same
US10566338B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2018 |
| Grant date | Feb 18, 2020 |
| Priority date | — |
| Expiry date | Mar 15, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
Abstract
Provided are a three-dimensional semiconductor memory device and a method of fabricating the same. The device may include a substrate including a peripheral circuit region and a cell array region, peripheral gate stacks provided on the peripheral circuit region of the substrate, and an electrode structure provided on the cell array region of the substrate. The electrode structure may include a lower electrode, a lower insulating layer covering the lower electrode, and upper electrodes and upper insulating layers, which are vertically and alternately stacked on the lower insulating layer. The lower insulating layer may be extended from the cell array region to the peripheral circuit region to cover the peripheral gate stacks, and a top surface of the lower insulating layer may be higher on the peripheral circuit region than on the cell array region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.