Semiconductor memory devices including a stress relief region
US10566342B2 · kind B2 · utility
1Cited by
7References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 7, 2017 |
| Grant date | Feb 18, 2020 |
| Priority date | — |
| Expiry date | Nov 7, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Semiconductor memory devices are provided. A semiconductor memory device includes a memory cell region and an insulator on a portion of the memory cell region. The semiconductor memory device includes a stress relief material that is in the insulator and is between the memory cell region and another region of the semiconductor memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.