Via support structure under pad areas for BSI bondability improvement

US10566374B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Sin-Yao Huang · Tainan, TW
• Ching-Chun Wang · Tainan, TW
• Dun-Nian Yaung · Taipei, TW
• Feng-Chi Hung · Kaohsiung, TW

Key dates

• Filing date: Oct 23, 2018
• Grant date: Feb 18, 2020
• Expiry date: Oct 23, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10F39/809

Abstract

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a substrate and a first interconnect wire arranged within a dielectric structure on the substrate. A bond pad contacts the first interconnect wire. A via support structure has one or more vias arranged within the dielectric structure at a location separated from the substrate by the first interconnect wire, The via support structure has a metal pattern density that is greater than or equal to approximately 19% and that is configured to mitigate damage caused by a force of a bonding process on the bond pad.