Integrated circuit and method of manufacturing integrated circuit
US10566941B2 · kind B2 · utility
1Cited by
3References
32Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 25, 2018 |
| Grant date | Feb 18, 2020 |
| Priority date | — |
| Expiry date | Jul 25, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/18
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit having a plurality of miniaturized transistors, wherein the plurality of transistors include: high concentration transistors which include channel regions having impurity concentrations of a first concentration; and low concentration transistors which include channel regions having impurity concentrations of a second concentration lower than the first concentration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.