Use of a raw oscillator and frequency locked loop to quicken lock time of frequency locked loop

US10566980B2 · kind B2 · utility

Assignee

• STMicroelectronics International N.V. · NL

Inventors

• Nitin Gupta · Savanuru, IN
• Jeet Narayan Tiwari · Greater Noida, IN

Key dates

• Filing date: Mar 19, 2018
• Grant date: Feb 18, 2020
• Expiry date: Apr 24, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03L2207/50
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

Disclosed is a method of locking a locked loop quickly, including receiving an input signal having an input frequency, and generating an intermediate signal having an intermediate frequency intended to be equal to a geometric mean of the input frequency and a desired frequency, but not equal. Results of division of the desired output frequency by the intermediate frequency are estimated, producing a first divider value. A first locked loop utilizing a controllable oscillator is activated. A divider value of the first locked loop is set to the first divider value, and the intermediate signal is provided to the first locked loop, so that when the first locked loop reaches lock, the controllable oscillator produces the desired frequency. When the first locked loop reaches lock, a second locked loop that utilizes the controllable oscillator is activated, the first locked loop is deactivated, and generation of the intermediate signal is ceased.