Transparent film error correction pattern in wafer geometry system
US10571248B2 · kind B2 · utility
1Cited by
4References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2017 |
| Grant date | Feb 25, 2020 |
| Priority date | — |
| Expiry date | Jul 13, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01B2210/56
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system includes one or more wafer geometry measurement tools configured to obtain geometry measurements from a wafer. The system also includes one or more processors in communication with the one or more wafer geometry measurement tools. The one or more processors are configured to apply a correction model to correct the geometry measurements obtained by the one or more wafer geometry measurement tools. The correction model is configured to correct measurement errors caused by a transparent film positioned on the wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.