Memory network with memory nodes controlling memory accesses in the memory network
US10572150B2 · kind B2 · utility
2Cited by
5References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2013 |
| Grant date | Feb 25, 2020 |
| Priority date | — |
| Expiry date | Apr 16, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to an example, a memory network includes memory nodes. The memory nodes may each include memory and control logic. The control logic may operate the memory node as a destination for a memory access invoked by a processor connected to the memory network and may operate the memory node as a router to route data or memory access commands to a destination in the memory network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.