High operation frequency, area efficient and cost effective content addressable memory architecture
US10572440B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2017 |
| Grant date | Feb 25, 2020 |
| Priority date | — |
| Expiry date | Mar 30, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1041
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various embodiments provide a content addressable memory (CAM) architecture that utilizes non-bit addressable memory, such as a single or dual port random access memory. The CAM includes a first non-bit addressable memory, a second non-bit addressable memory, a multiplexer, a write operation encoder, a read operation encoder, and a match signal generator. In contrast to bit addressable memories, non-bit addressable memories are widely available, have high performance frequency, and are area efficient as compared to bit addressable memories. Accordingly, the CAM architecture described herein has low costs and time to market, increased processing time, and improved area efficiency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.