Patent · US Active

System and method for generation of an integrated circuit design

US10572617B2 · kind B2 · utility

0Cited by

14References

10Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Carsten Greiner · Holzgerlingen, DE
Gerrit Koch · Herrenberg, DE
Johannes C. Reichart · Highland, US
Ralf Winkelmann · Eppelheim, DE

Key dates

Filing date	Oct 26, 2017
Grant date	Feb 25, 2020
Priority date	—
Expiry date	Oct 26, 2037

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/333
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method for verification of a design of an electronic circuit is provided. The method includes executing test runs of the design. The method further includes increasing a fail counter if the executing of a test run of the test runs failed. The method further includes increasing a pass counter if the executing of the test run of the test runs passed. The method further includes halting the executing of the test runs of the design if the current ratio of the fail counter versus the pass counter exceeds a predetermined threshold.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.