Patent · US Active

Pseudo-asynchronous digital circuit design

US10572619B2 · kind B2 · utility

4Cited by

9References

18Claims

0Family size

Assignee

Bar-Ilan University · IL

Inventors

Itamar Levi · al-Araqeeb, IL
Osnat Keren · Rosh HaAyin, IL
Alexander Fish · Even Yehuda, IL

Key dates

Filing date	Jun 29, 2017
Grant date	Feb 25, 2020
Priority date	—
Expiry date	Jun 29, 2037

Classification

Technology area (CPC G)Physics
CPC primaryG06F2221/034
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A logic element includes a logic block, a clock generator, a clock assigner and at least one sampling element. The logic block implements a logic function on input data to obtain a plurality output data signals. The output data signals are sampled by respective clock signals. The clock generator generates phase-shifted clock signals from a reference clock signal. The clock assigner assigns differing ones of the phase-shifted clock signals to respective output data signals. The sampling element(s) sample the output data signals in accordance with the respective assigned phase-shifted clock signals.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.