Package structure and manufacturing method thereof
US10573587B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2017 |
| Grant date | Feb 25, 2020 |
| Priority date | — |
| Expiry date | Aug 10, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/81191
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A package structure includes a redistribution layer, a chip, an encapsulant, an under bump supporting layer, an attachment layer and solder balls. The redistribution layer includes a first surface, a second surface opposite to the first surface and a patterned circuit layer disposed on the first surface, wherein an outer surface of the patterned circuit layer and the first surface are coplanar. The chip is disposed on the second surface and electrically connected to the patterned circuit layer. The encapsulant is disposed on the second surface to encapsulate the chip. The under bump supporting layer is disposed on the first surface and includes openings for exposing the outer surface. The attachment layer covers the inner surface of each opening and the exposed portion of the patterned circuit layer. The solder balls are disposed in the openings respectively and electrically connected to the patterned circuit layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.