Three dimensional integrated circuit
US10573627B2 · kind B2 · utility
11Cited by
49References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 7, 2018 |
| Grant date | Feb 25, 2020 |
| Priority date | — |
| Expiry date | Aug 7, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Implanting ions to form a cleave layer in a semiconductor device causes damage to sensitive materials such as high-K dielectrics. In a process for forming a cleave layer and repairing damage caused by ion implantation, ions are implanted through a circuit layer of a substrate to form a cleave plane. The substrate is exposed to a hydrogen gas mixture for a first time at a first temperature to repair damage caused by the implanted ions. A cleaving process may then be performed, and the cleaved substrate may be stacked in a 3DIC structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.