Physically unclonable camouflage structure and methods for fabricating same
US10574237B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2017 |
| Grant date | Feb 25, 2020 |
| Priority date | — |
| Expiry date | Aug 11, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/907
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An application specific integrated circuit (ASIC) and a method for its design and fabrication is disclosed. In one embodiment, the camouflaged application specific integrated circuit (ASIC), comprises a plurality of interconnected functional logic cells that together perform one or more ASIC logical functions, wherein the functional logic cells comprise a camouflage cell including: a source region of a first conductivity type, a drain region of the first conductivity type, and a camouflage region of a second conductivity type disposed between the source region and the drain region. The camouflage region renders the camouflage cell always off in a first camouflage cell configuration and always on in a second camouflage cell configuration having a planar layout substantially indistinguishable from the first configuration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.