Effective address based instruction fetch unit for out of order processors
US10579384B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 8, 2017 |
| Grant date | Mar 3, 2020 |
| Priority date | — |
| Expiry date | Apr 27, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/682
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects of the invention include a computer-implemented method for executing one or more instructions by a processing unit. The method includes receiving, by an instruction fetch unit (IFU), a request to fetch an instruction for execution, wherein the instruction includes an effective address (EA). The IFU can further access an instruction cache directory (I-directory) using the EA of the requested instruction to determine whether the EA of the requested instruction matches an EA stored in an associated instruction cache (I-cache). An instruction cache (I-cache) can output the requested instruction in response to or based at least in part on determining that the requested instruction EA matches an entry in the I-cache. A decode unit can decode the requested instruction output by the I-cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.