Robert Alan Philhower
22Patents
7h-index
41Co-inventors
69Inventor score
Filing activity: May 2, 1997 → Mar 30, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6131182A | Method and apparatus for synthesizing and optimizing control logic based on SRCMOS logic array macros | Physics | 51 | Expired |
| US7512772B2 | Soft error handling in microprocessors | Physics | 26 | Active |
| US7627742B2 | Method and apparatus for conserving power by throttling instruction fetching when a processor encounters low confidence branches in an information handling system | Physics | 17 | Active |
| US7401242B2 | Dynamic power management in a processor design | Emerging Cross-Sectional Technologies | 15 | Active |
| US7490224B2 | Time-of-life counter design for handling instruction flushes from a queue | Physics | 11 | Active |
| US7681056B2 | Dynamic power management in a processor design | Emerging Cross-Sectional Technologies | 7 | Active |
| US8255669B2 | Method and apparatus for thread priority control in a multi-threaded processor based upon branch issue information including branch confidence information | Physics | 7 | Active |
| US8006070B2 | Method and apparatus for inhibiting fetch throttling when a processor encounters a low confidence branch instruction in an information handling system | Physics | 7 | Active |
| US7925853B2 | Method and apparatus for controlling memory array gating when a processor executes a low confidence branch instruction in an information handling system | Emerging Cross-Sectional Technologies | 7 | Active |
| US6785703B2 | Simultaneous dual rail static carry-save-adder circuit using silicon on insulator technology | Physics | 5 | Expired |
| US7797521B2 | Method, system, and computer program product for path-correlated indirect address predictions | Physics | 4 | Active |
| US6711633B2 | 4:2 compressor circuit for use in an arithmetic unit | Physics | 3 | Expired |
| US11157280B2 | Dynamic fusion based on operand size | Physics | 2 | Active |
| US7913070B2 | Time-of-life counter for handling instruction flushes from a queue | Physics | 2 | Active |
| US7725659B2 | Alignment of cache fetch return data relative to a thread | Physics | 2 | Active |
| US7370176B2 | System and method for high frequency stall design | Physics | 1 | Expired |
| US9996351B2 | Power management of branch predictors in a computer processor | Emerging Cross-Sectional Technologies | 1 | Active |
| US10579384B2 | Effective address based instruction fetch unit for out of order processors | Physics | 1 | Active |
| US10037207B2 | Power management of branch predictors in a computer processor | Emerging Cross-Sectional Technologies | 1 | Active |
| US10740104B2 | Tagging target branch predictors with context with index modification and late stop fetch on tag mismatch | Physics | 0 | Active |
| US11074379B2 | Multi-cycle latch tree synthesis | Physics | 0 | Active |
| US10552159B2 | Power management of branch predictors in a computer processor | Emerging Cross-Sectional Technologies | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.