Wafer level packaging with integrated antenna structures
US10580745B1 · kind B1 · utility
2Cited by
4References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2018 |
| Grant date | Mar 3, 2020 |
| Priority date | — |
| Expiry date | Aug 31, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/12105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
RF semiconductor chips may be packaged on wafer level on the basis of a two-step process for providing a package material, thereby providing very short electrical connections between antenna structures formed in the package material and the semiconductor chip. In some illustrative embodiments, the antenna structures may be provided above the semiconductor chip, which results in a very space-efficient overall configuration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.