Integrated circuit (IC) chip arrangement
US10580762B1 · kind B1 · utility
0Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2018 |
| Grant date | Mar 3, 2020 |
| Priority date | — |
| Expiry date | Oct 25, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Examples disclosed herein involve integrated circuit chip arrangements. An example integrated circuit (IC) package may include a first semiconductor chip that includes a first metal-oxide-semiconductor field-effect transistor (MOSFET) and a second semiconductor chip mounted within a housing of the IC package. The second semiconductor chip may include a second MOSFET and a control circuit configured with a first driver for the first MOSFET and a second driver for the second MOSFET. The first semiconductor chip may be mounted to the second semiconductor chip opposite a base of the IC package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.